Field of the Invention
The present invention relates generally to nonvolatile semiconductor memories, and more particularly the invention relates to nonvolatile semiconductor memories having boosting lines self-aligned with underlying word lines.
Nonvolatile semiconductor memories, i.e., flash memories, such as flash electrically erasable/programmable read only memories (hereinafter referred to as EPROMs or EEPROMs), have been developed for use as high-density memory media in devices such as portable terminals, digital cameras, portable computer cards and the like. It would be desirable to reduce the manufacturing cost per bit and operational power consumption in those high-density memory media. It is particularly important to reduce the power consumption since a large amount of data, for example, at least a block data, is erased/programmed at one time in flash memories.
Conventional flash memories typically include a charge pump circuit, i.e., a voltage multiplier circuit, which is used to generate a program voltage higher than a power supply voltage during its programming operation. Reducing the program voltage can be a major factor in reducing the chip area and the power consumption.
A typical memory cell includes a transistor comprising drain and source regions on one surface of a semiconductor substrate with a channel region therebetween. A floating gate is formed over the channel region through a gate oxide layer, and a control gate is formed over the floating gate through a dielectric layer. Two approaches have been used to erase/program the memory cell transistor. One approach is a hot electron injection approach in which hot electrons accelerated by a potential applied across the drain and source regions are injected into the floating gate by a high voltage applied to the control gate. The other approach is a Fowler-Nordheim tunnelling (hereinafter referred to as a F-N tunnelling) process in which electrons are tunnelled into/from the floating gate by application of a high voltage to the control gate, drain, source or substrate.
Hot electron injection memory cell transistors generate more electrical current than F-N tunnelling memory cell transistors, and they need one bit line contact per cell. Such an increase of the number of contacts inhibits the reduction of chip area and therefore inhibits the reduction in bit cost per cell. On the other hand, although memory cell transistors using the F-N tunnelling process consume less electrical power than those using hot electron injection, they require a voltage higher than that required in hot electron injection. However, the chip area may be readily reduced by one bit line contact for a plurality of series-connected memory cell transistors. The F-N tunnelling approach is therefore widely used in a NAND-type flash memory cell array in which a plurality of series-connected memory cell transistors are connected to a corresponding bit line. The hot electron injection approach is widely used in a NOR-type flash memory cell array in which a plurality of memory cell transistors are connected in parallel between each of a plurality of bit lines and a ground source line.
In NAND-type flash memory, one prior approach to reducing the program voltage is disclosed in an article entitled, "A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-down and Zero Program Disturbance," published in 1996 Symposium on VLSI Technology, pp. 238-239, which corresponds to U.S. application Ser. No. 08/824,483, assigned to the assignee of the present invention. In the device described therein, a plurality of memory strings, each of which includes a plurality of memory cell transistors whose source-drain paths are connected in series on one surface of a semiconductor substrate, are arranged in a matrix configuration of rows and columns. After formation of a conventional NAND-type memory cell array in which control gates of memory cell transistors in each row are connected to a corresponding one of word lines, a program booster plate is formed through a dielectric layer over memory cell transistors of each memory block defined as memory strings in each row. During programming, a boosting voltage applied to the program booster plate may allow a program voltage applied to control gates of a selected word line to be lowered due to a voltage self-boosted to the control gates thereof.
However, since the prior art program booster plate in each memory block is formed on thin plate dielectric layers on the control gates therein, side-wall insulating layers of underlying floating gates and insulating layers on source and drain regions therein, it takes considerable time to charge/discharge the boosting voltage into/from the booster plate, thereby increasing the programming period. Moreover, during its fabrication process, fabrication defects in any one of the insulating layers cause the boosting voltage to be applied to a source, drain, floating gate or control gate of a memory transistor associated therewith. Thus, the memory block associated therewith may malfunction.